This blog article presents how Placer can be used on a real-world use case. In particular, it provides
information to an embedded application developer for exploring quickly the optimal placement and
schedule of the tasks computed by an embedded application named AquaScan. Alternatively, Placer
can also handle additional placement constraints to let the developer study the impact on time
performance in case the optimal placement and schedule are not followed.
Designing and developing optimal software architectures for embedded applications to execute on a
set of heterogeneous hardware devices in best time and energy performance requires making
complex decisions. In particular, decision on placing software components on the appropriate
hardware processing devices must not just consider processing performance but also data transfer.
On multi-core and many-core devices, there is not much constraint on the code writing exercise. On
the other hand, when GPU and FPGA are available in an embedded device then specific code must be
developed for these types of hardware. Determining what software components would benefit most
from executing on GPU or FPGA is extremely hard. Mainly because it is not always the obvious
heavily parallelisable software task of an application that should automatically be placed on GPU or
FPGA. The type and size of data transfer must be considered to make an optimal placement decision.
Otherwise what may seem like a judicious placement thanks to a heavy parallelisation in the
processing could not yield the optimal execution if for instance, datasets are large and do not form a
Furthermore, next to time performance, in embedded systems composed of several devices where
some run on battery while others are powered through a UPC, energy consumption must be taken
into account in particular for battery-operated devices. Thus, even expert developers cannot answer
whether or not a given software component placement and software task schedule provide the most
appropriate trade-off between time and energy performance.
To ease this work, TANGO has developed two design tools. The first tool named DTC-Poroto helps to
quickly port C code to VHDL and to take time and energy measure to characterise a software task
execution on various input datasets. The second tool named Placer, takes a model of hardware
processing, storage and transfer capabilities alongside a model of computation and communication
(MoCC) of software tasks and their data exchange. The MoCC provided by Placer makes it possibility
for a software task to provide several implementations, for instance, for executing on different
hardware processing element such as CPU, GPU or FPGA. Furthermore, the MoCC is augmented with
different software task dependencies information as well as other properties such as time and
energy performance of each task implementation on a given hardware. From these input models,
Placer computes the optimal placement and schedule of software task on the given hardware
In the remaining of this article, the application named AquaScan described very briefly below is used
to illustrate the use of Placer. A future Blog article will be dedicated to DTC-Poroto.
For more information, find attached the full document!